Chris Hodges
Backline is built into PennyLane and Catalyst and lets developers define quantum-classical workloads from a Python frontend, then compile them through MLIR for execution across heterogeneous hardware. The framework supports both local and distributed targets.
The most interesting part is the latency. In testing, Xanadu used an AMD VPK120 FPGA board as the controller and RoCE v2 for communication. Across roughly 1 million communication rounds per path, the system achieved median steady-state round-trip latency of:
- 2.305 µs → AMD Ryzen Threadripper PRO CPU
- 4.5 µs → AMD Instinct MI210 GPU
That means the CPU communication path completed a full round trip in about 2.3 millionths of a second.
Why Backline Matters
Fault-tolerant quantum computers will require substantial classical compute around the QPU.
A typical loop looks like:
QPU → measurement → FPGA/CPU/GPU → correction/control → QPU
This is particularly important for quantum error correction (QEC), where measurement results must be processed and fed back into the quantum system with extremely low latency.
Python is convenient for developing quantum algorithms, but interpreted execution isn't suitable for these real-time paths. Backline addresses this by letting developers describe workloads at a high level while compiling the performance-critical sections for CPUs, GPUs and FPGAs.
The architecture effectively separates developer interface from execution hardware:
Python → PennyLane/Catalyst → MLIR → CPU / GPU / FPGA
Developers therefore don't need to write an entire application around FPGA-specific or accelerator-specific programming models.
AMD Is Building the Classical Side of Quantum Computing
Backline fits directly into AMD's broader quantum strategy. AMD expects quantum processors to operate as specialized accelerators inside heterogeneous systems rather than replace classical processors. Its quantum stack already includes EPYC CPUs, Instinct GPUs, Versal adaptive SoCs/FPGAs, Pensando networking and open software infrastructure.
Xanadu and AMD have already demonstrated this model at the application level. In March 2026, they ran a hybrid quantum-classical aerospace CFD workload using PennyLane and AMD infrastructure. The experiment involved a 256 × 256 matrix, 20 qubits and approximately 35 million quantum gates.
PennyLane's Lightning simulator also supports AMD GPUs through lightning.amdgpu, allowing developers to move quantum simulations from CPU execution to AMD GPU acceleration with essentially a backend change.
From Quantum Algorithms to Heterogeneous Systems
Backline highlights an important shift in quantum computing. The bottleneck isn't just the number of qubits. Large-scale systems also need fast classical processing for control, calibration, orchestration, simulation, data preparation, post-processing and error correction. AMD expects these classical compute requirements to increase as quantum processors scale.
Backline attacks the communication and programming layer between those processors.
The resulting architecture looks less like a standalone quantum computer and more like a heterogeneous supercomputer:
QPU + FPGA + CPU + GPU + high-speed networking
And the headline number is concrete: 2.305 µs median round-trip latency between an AMD FPGA controller and Threadripper PRO CPU across roughly one million rounds.
Chris Hodges
